As a member of the DFP (Design For Power) team you will be responsible for developing and defining low power implementation and EMIR signoff methodology of world class chips under most advanced tech node. Your responsibilities may include, but not be limited to:

· Developing physical design flow which including the construction of power delivery network, building of multi-voltage and power gating design, power aware optimization etc.
· Defining EMIR signoff methodology at block & chip level, including signoff corner, analysis condition, signoff target and criteria etc. Conducting hotspot/grid weakness study and providing improvement plan
· Engaging closely with front-end power team on power estimation and fullchip power budgeting
· Working closely with package/PISI team for system level IR convergence for all analog/digital domains and be the 'go-to' person for cross team deliverables
· Driving low power design and verification closure by engaging with design/synthesis teams on optimizing chip power structure and power intent to manage physical design risks
· Working with EDA vendors to resolve tool issues and drive improvements in design convergence and signoff
· Leading full chip EMIR sign-off, monitor EMIR status and manage risks at each milestone to meet tapeout schedule
· Driving silicon correlation with a continuous plan to optimize timing/EMIR signoff margin
· Empowering physical design engineers to create industry leading chips by providing guidelines on PPA improvement plan from DFP perspective