Responsibility: BE design of Analog-IP or Std-cell（layout design & verification, BE -lib design) Qualification: 1) Understanding semiconductor process and device structure 2) Fimiliar with Virtuoso, Calibre tools 3）Experienced at amalog IP or Std-cell layout design 4)Experience in 28nm and below processes is preferred 5)Be practical and conscientious and have a sense of responsibility. 6)Able to communicate and collaborate well with other team members.