Free
Asic Layout Engineer_rbcn/ae, Shanghai
China, 上海, 上海,
发表 November 21, 2023
描述
Job Description layout of IC analog modules layout verification and finishing lead large analog module layout Qualifications master or bachelor’s degree in microelectronics or other related subjects >= 3ys experience in IC analog layout ability to finish module-level analog layout independently ability to lead large-module analog layout ability to understand top level floor plan good understanding of semiconductor physics process and basic concept of different devices familiar with Cadence/Mentor based tools flexibility and good capacity for communication and teamwork foreign languages: English